The number of multimedia systems is increasing with the gradual increase of CPU data processing speed. Accordingly, with higher integration of semiconductor memory devices, increasing a bandwidth of a synchronous memory device is desired for improving operating speed of the semiconductor memory device.
For example, a DDR (double data rate) synchronous memory device consecutively processes two data units for one clock period with synchronization to both the rising and falling edges of an external clock signal. Thus, the DDR synchronous memory device has double bandwidth from an SDR (single data rate) synchronous memory device for increased operating speed.
For accurate timing of input and output data in the DDR synchronous memory device according to specifications of data set-up time and hold time at a destination, a data strobe signal DQS is input with data. A DQS generated for a data write operation in the DDR synchronous memory device is referred to as a write data strobe signal WDQS.
The WDQS is at a logic low state “0” before a predetermined clock cycle such as at one clock cycle 1 tCK from when a write command is generated when the WDQS makes a low to high transition as data is input. The WDQS is clocked with respect to the clock signal as data is input and transitions to the logic high state after the data is all input. The “tCK” indicates one clock cycle of the external clock signal CLK.
Such data is input with tuning of a set-up time and a hold time with respect to the single external WDQS and is stored in the DDR synchronous memory device. A time period from the rising edge of the clock signal CLK at which an external write command is input to a first rising edge of the WDQS when a first data is input, is referred to tDQSS. The range between maximum and minimum values of the tDQSS (such as a range of 1 tCK for example) is set for ensuring a stable write operation in the DDR synchronous memory device and so that the WDQS is activated at an accurate time.
FIG. 1 is a timing diagram showing the minimum value tDQSS(MIN) and the maximum value tDQSS(MAX) of the tDQSS in the DDR synchronous memory device. Referring to FIG. 1, when the I/O is for a POD (pseudo open drain), a DQS before preamble and a DQS after postamble is maintained in a logic low state with each being for a half clock cycle (0.5 tCK). In FIG. 1, the tDQSS(MIN) is 0.5 tCK, and the tDQSS(MAX) is 1.5 tCK such that a tDQSS margin is 1 tCK.
FIG. 2 shows a block diagram of an input data alignment circuit 200 supporting 4 bits pre-fetch in a conventional DDR synchronous memory device. FIG. 3 is a timing diagram of signals during operation of the data alignment circuit 200 of FIG. 2. Referring to FIGS. 2 and 3, the input data alignment circuit 200 includes a data buffer 203, a data strobe buffer 205, a clock buffer 207, a first sampler 212, a second sampler 214, an internal write clock generation unit 220, a tree block 230, an internal clock sync delay block 240, an alignment block 250, and a decision block 260.
The data buffer 203 buffers data DQ input from a source external to the DDR synchronous memory device. The data strobe buffer 205 buffers the WDQS also input from the external source to generate an internal data strobe signal DSS. The clock buffer 207 buffers a clock signal CLK input from the external source to generate a buffered internal clock signal ICLK.
The first sampler 212 samples the data DQ from the data buffer 203 in response to a first edge, such as rising edges for example, of the DSS. The second sampler 214 samples the DQ from the data buffer 203 in response to a second edge, such as falling edges for example, of the DSS. Each of a first data DF and a second data DS sampled by the first sampler 212 and the second sampler 214, respectively, have a data window of 1 tCK as shown in FIG. 3.
The internal write clock generation unit 220 generates an internal write clock signal PCLK from ICLK and a write command signal WCMD from the external source. PCLK is supplied to the decision block 260 through the tree block 230. The tree block 230 is comprised of a series of plurality of inverters (not shown) for delaying PCLK for a predetermined first delay time to generate a delayed internal write clock signal PCLKD.
The internal clock sync delay block 240 includes a first sync delay unit 242, a second sync delay unit 244, and a third sync delay unit 246. The first sync delay unit 242 delays the first data DF for the predetermined first delay time to generate a delayed first data DDF. The second sync delay unit 244 delays the second data DS for the predetermined first delay time to generate a delayed second data DDS. Also, the third sync delay unit 246 delays the DSS for the predetermined first delay time to generate a delayed internal data strobe signal DDSS. In this manner, the internal clock sync delay unit 240 synchronizes the DDF, the DDS, and the DDSS with PCLKD.
The alignment block 250 aligns each data of the DDF and DDS into 4 bits parallel data DDF1, DDS1, DDF2, and DDS2 as shown in FIG. 3 synchronized to DDSS such as synchronized to falling edges of DDSS in a DQS domain state. The decision block 260 selects from groups of parallel data DDF1, DDS1, DDF2, and DDS2 in synchronism to PCLKD to generate valid data. Thus, the decision block 260 changes the DQS domain state of DDF1, DDS1, DDF2, and DDS2 to a domain state of the PCLKD.
The decision block 260 decides the minimum/maximum values of the tDQSS, that is, a tDQSS margin, with respect to each bit data of the DDF1, DDS1, DDF2, and DDS2 based on the PCLKD. Accordingly, during a write operation with a burst length (BL) of 4, the conventional data alignment circuit 200 with 4 bits pre-fetch generates at least 4 tDQSS maximum/minimum value decision points with respect to each DDF1, DDS1, DDF2, and DDS2 for each DQ pin. For example, at least a total of 128 tDQSS maximum/minimum value decision points are generated with respect to a graphic semiconductor memory device having 32 DQ pins during a write operation with a burst length of 4.
The maximum and minimum values of the tDQSS define the margin between PCLKD and each of DDF1, DDS1, DDF2, and DDS2 in the PCLK domain state. In general, the maximum and minimum values of the tDQSS are each a predetermined value such as 0.5 tCK from a center point of a PCLKD window. In FIG. 3, since PCLKD has a window of 1 tCK, the tDQSS maximum/minimum values for each bit data of DDF1, DDS1, DDF2, and DDS2 is ideally 0.5 tCK such that the tDQSS margin is 1 tCK.
However, the tDQSS margin may not actually be 1 tCK due to skew between data lines, power noise, and a plurality of tDQSS maximum/minimum value decision points. As the clock frequency increases, the preset tDQSS maximum/minimum values may become insufficient resulting in restriction to the write operation. Accordingly, a wider tDQSS margin is desired with increased tDQSS maximum/minimum values.
A predetermined write delay time tCCD (column address strobe command delay) exists between write commands (such as WR1, WR2, and WR3 in FIG. 3) to the semiconductor memory device. For example in FIG. 3, when tCCD=2 tCK, a third write command WR3 has a write gap. An invalid write strobe signal (invalid WDQS) may be generated from the WR3 command with the write gap as shown in FIG. 3. Such an invalid WDQS may result in invalid data such as DIN0 or DIN1 being sampled into the memory device. A mechanism for eliminating such invalid data is desired.